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    Russian Electronics: Semiconductor and Processors

    Kiko
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    Post  Kiko Mon Dec 20, 2021 12:37 am

    Russian scientists have created a chip for a new generation of photonic technology

    Scientists from the Moscow Institute of Electronic Technology (MIET) and the Moscow State Pedagogical University (MPGU), together with other Russian scientists, have created a chip for developing a new generation of photonic circuits. Experts say that the developed technology for the manufacture of non-volatile reconfigurable nanophotonic chips is ready for implementation in microelectronic production without additional upgrades.

    A team of scientists from MIET and Moscow State Pedagogical University has created fully optical tunable ring microcavities based on silicon nitride and thin films of one of the so-called phase memory materials - Ge-Sb-Te (GST). The main feature of these materials is the change in optical and electrical properties when switching between amorphous (disordered) and crystalline (ordered) states.

    “In the chip we have developed, the surface of silicon nitride ring microcavities is locally covered with a thin GST film. A change in the phase state of the GST coating and, consequently, its absorption, leads to a change in the optical signal passing through the waveguide. The switching of phase states can be initiated by laser pulses passing through the waveguide, ”said Petr Lazarenko, senior researcher at the Institute of Advanced Materials and Technologies, MIET.

    Phase switching occurs in 10 nanoseconds, and the GST film is one of the most optimal materials for controlling signals in thin-film waveguide elements used in telecommunication devices.

    According to the specialists of the scientific group, the technology they have developed for the manufacture of non-volatile reconfigurable nanophotonic chips is completely ready for implementation in microelectronic production, since it can be fully implemented using standard CMOS technology processes and does not require additional modernization of installations.

    Now the research team is optimizing the chip to increase the number of written logic levels. Also, the research group develops approaches to the design of new integrated-optical circuits and systems based on them.

    https://sdelanounas.ru/blogs/144962/

    GarryB, dino00, Big_Gazza, kvs, x_54_u43, miketheterrible, thegopnik and LMFS like this post

    miketheterrible
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    Post  miketheterrible Mon Dec 20, 2021 10:26 am

    Sorry, had to resort to a Twitter post:

    Baikal-S, a 48 arm processor that also uses RISC-V coprocessor.

    https://mobile.twitter.com/torgeek/status/1472571292360626186

    GarryB, kvs and lancelot like this post

    lancelot
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    Post  lancelot Mon Dec 27, 2021 8:51 am

    https://www.tomshardware.com/news/russias-biggest-bank-tests-elbrus-cpu-finds-it-unacceptable

    Every server begins from its chassis and some general features such as remote management, which Sber evaluates under its Functional Testing procedure. Apparently, an MCST Elbrus-8C machine failed 84% of Sber's Functional Testing as it could not be easily removed from the rack, lacked proper LED indicators, and came without remote management, which to a large degree made it unusable for usage in commercial datacenters. There is some hope, though.

    "One of the surprising things about the Elbrus-8C server was that it is a real product," said Zhbankov. "It was a real server that we were given. […] It is an actual product that has its disadvantages, loads of disadvantages, but we can work with them."

    Elbrus-8C Evaluation Summary
    4-way Elbrus-8C vs 2-way Intel Xeon Gold 6230
    SPEC CPU 2017 2.62 (base) ~ 3.15 (peak) times slower
    PGbench/PostreSQL 1.7 (read only profile) ~ 3.3 (read write profile) times lower
    Java 23 ~ 26 times higher response time

    To be honest I expected worse given it is a 28nm vs 14nm processor.
    Given Elbrus is VLIW, and not that suited for multi-threaded workloads like a bank would use, but more for peak FP compute I think it did ok.

    Sber basically has an issue with the lack of suitability of the server they were provided with for rack mount and remote service. That is an issue of the platform not the CPU design itself. The poor Java performance might be a lot of things like having less and slower memory or the low amount of threads on each core.

    I think a bank would be better off with the Baikal line of processors though. Short and small core with multiple threads is better than Wide and large core with wide FP units for a bank running SQL and Java loads.

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    Singular_Transform
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    Post  Singular_Transform Mon Dec 27, 2021 1:19 pm

    lancelot wrote:

    To be honest I expected worse given it is a 28nm vs 14nm processor.
    Given Elbrus is VLIW, and not that suited for multi-threaded workloads like a bank would use, but more for peak FP compute I think it did ok.

    Sber basically has an issue with the lack of suitability of the server they were provided with for rack mount and remote service. That is an issue of the platform not the CPU design itself. The poor Java performance might be a lot of things like having less and slower memory or the low amount of threads on each core.

    I think a bank would be better off with the Baikal line of processors though. Short and small core with multiple threads is better than Wide and large core with wide FP units for a bank running SQL and Java loads.


    It is a good news, they started to push the CPU to wider application, like datacenters.

    Main problem here is the Elbrus needs new linux kernel and application library, it is not a native x86 CPU, needs to translate the instructions.


    And these tests compared a 20 core CPU again an 8 core one, means the results are the expected one. They need to put two CPU into each server, and even that will be cheaper, considering the Elbrus die size fraction of the Xeon.
    Scorpius
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    Post  Scorpius Mon Dec 27, 2021 3:31 pm

    miketheterrible wrote:Sorry, had to resort to a Twitter post:

    Baikal-S, a 48 arm processor that also uses RISC-V coprocessor.

    https://mobile.twitter.com/torgeek/status/1472571292360626186

    here is a link to the specifications from the manufacturer's website:
    https://www.baikalelectronics.com/products/4429/

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    miketheterrible
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    Post  miketheterrible Mon Dec 27, 2021 3:49 pm

    Singular_Transform wrote:
    lancelot wrote:

    To be honest I expected worse given it is a 28nm vs 14nm processor.
    Given Elbrus is VLIW, and not that suited for multi-threaded workloads like a bank would use, but more for peak FP compute I think it did ok.

    Sber basically has an issue with the lack of suitability of the server they were provided with for rack mount and remote service. That is an issue of the platform not the CPU design itself. The poor Java performance might be a lot of things like having less and slower memory or the low amount of threads on each core.

    I think a bank would be better off with the Baikal line of processors though. Short and small core with multiple threads is better than Wide and large core with wide FP units for a bank running SQL and Java loads.


    It is a good news, they started to push the CPU to wider application, like datacenters.

    Main problem here is the Elbrus needs new linux kernel and application library, it is not a native x86 CPU, needs to translate the instructions.


    And these tests compared a 20 core CPU again an 8 core one, means the results are the expected one. They need to put two CPU into each server, and even that will be cheaper, considering the Elbrus die size fraction of the Xeon.

    Even the replies in the comment section mentioned Tom's Hardware being misleading and that there is general praise of the architecture and design.

    As you said, the bank is being retarded and comparing a much larger core cpu to an 8 core one. Mind you, there are specific things that is needed that banks need and they may not be as tech savvy.  But ultimately, the issues seen here isn't really cpu dependent.

    The ram in question is ddr3 ecc reg memory.  Remote management and the likes isn't cpu bound these days and requires a secondary card or something like HP's HPE iLO that we use at our work.  But as someone quoted in comment section, it doesn't have to do with CPU.

    Elbrus has Elbrus OS which has its own library.  Maybe needs more work.
    miketheterrible
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    Post  miketheterrible Mon Dec 27, 2021 10:53 pm

    https://sdelanounas.ru/blogs/145008/

    This also has some benchmarks showing the Baikal S being quite the performance monster.
    GarryB
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    Post  GarryB Tue Dec 28, 2021 5:38 am

    Main problem here is the Elbrus needs new linux kernel and application library, it is not a native x86 CPU, needs to translate the instructions.

    Would think not being windows based would be expected and a requirement for hardware to be used by Russians.
    miketheterrible
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    Post  miketheterrible Mon Jan 03, 2022 7:10 am

    https://sdelanounas.ru/blogs/145143/

    Everyday life of a domestic developer: "Elbrus-16C"

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    miketheterrible
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    Post  miketheterrible Wed Jan 12, 2022 8:37 pm

    https://sdelanounas.ru/blogs/145251/

    Russian scientists have created the first domestic five-qubit integrated circuit

    Article mentions an Indian working for IBM who doubted Russia able to make such processors.  I guess he will be eating his words now?  I mean, IBM is the last to talk smack since majority of their development has gone nowhere.

    Russian scientists have created the first domestic five-qubit integrated circuit for quantum computing. MIPT specialists worked on it, and it is a full-fledged Russian prototype of a quantum processor that can be used in quantum machine learning. At the beginning of 2020, IBM CEO Arvind Krishna openly expressed doubts that Russia is capable of making a breakthrough in the field of quantum computing.

    Domestic quantum processor

    Russia has developed the first integrated circuit based on five superconducting qubits in a holder. It was created by specialists of the Moscow Institute of Physics and Technology (MIPT) in the Laboratory of Artificial Quantum Systems (LIKS), and, as representatives of the university told CNews, this development can be considered a prototype of a quantum processor.

    The developers of this multi-qubit system claim in their official announcement that it is unique and completely manageable. According to them, even at the current stage of development, it can be used in quantum machine learning — a separate field of science at the intersection of quantum physics and modern information processing technologies.

    Created in the MIPT laboratory, the integrated circuit was manufactured with the participation of employees of the Center for Collective Use (CCP). At the time of publication of the material, it passed a number of tests that showed that all its elements work exactly with the parameters that the developers expected.

    Six years of operation

    The first Russian qubit, according to a LIKS researcherAccording to Alexey Bolgar, it was obtained six years ago, in 2015, directly in this laboratory. According to him, after that, the laboratory staff and the CCP continued to work in this direction. "All these years, the staff of the MIPT Central Design Bureau and the laboratory have been working to improve the technology of manufacturing superconducting quantum structures with different architectures. As a result, we now have a technology that is already reliable enough to create multi-qubit computing devices. The integrated quantum circuit created by us, unlike the prototypes previously developed in Russia, allows us to fully control the state of all five qubits. Such integrated circuits are necessary for creating a universal quantum computer based on superconducting qubits. This is a great technological success, " said Alexey Bolgar.

    MIPT representatives noted that the creation of the Russian multi-qubit integrated circuit was made possible due to four factors, and the first of them is a significant improvement in the control of geometric and electrical parameters of tunnel contacts. According to representatives of the university, these contacts can be considered the "heart" of superconducting qubits, since the performance of the entire quantum circuit directly depends on the quality and reproducibility of their manufacture.

    The second factor is the adjustment of the manufacturing technology of microwave resonators, the quality factor of which in the single-photon mode is hundreds of thousands. This is also a very important part of quantum integrated circuits — they are needed to read the quantum state of qubits.

    The third factor is debugging the manufacturing process of" hanging bridges " (air bridge), which are necessary to suppress parasitic resonant modes, which has a positive effect on the Q-factor of structures. But the most important component that allowed MIPT specialists to create a multi-qubit system, in their opinion, is the experience they have accumulated in this area over the past few years.

    Future plans

    MIPT does not specify when exactly the era of Russian quantum computers will begin, nor does it disclose its future plans for the development of new multi-qubit integrated circuits and their implementation. According to Alexey Bolgar, who was directly involved in the development of the five-qubit scheme, for any further actions in this area, it is necessary to modernize both the CCP and the ICS laboratory as part of MIPT.

    "Our current results show that the technological and measurement capabilities of the CCP and our laboratory allow us to work out and complete all the steps necessary to create elements of quantum processors, from technological drawings to an integrated quantum circuit on a chip and its measurements. However, further development of work on the creation of controlled elements of the quantum computer and the computer itself will require modernization of the "clean zone" of the CCP and additional equipment of the laboratory with modern research equipment, " said Alexey Bolgar.
    ____________________________________________________________________________________________________________________________________________________________________________________________

    https://sdelanounas.ru/blogs/144962/#cut

    Russian scientists have created a chip for a new generation of photonic technology

    Manufactured tunable ring resonator based on silicon nitride and chalcogenide phase memory material. General view and schematic image of the ring resonator obtained using an optical microscope (a), a scanning electron microscope (b), and a 3d illustrator (c).

    Scientists of the Moscow Institute of Electronic Technology (MIET) and the Moscow State Pedagogical University (MSUU), together with other Russian scientists, have created a chip for developing new-generation photonic circuits. Experts say that the developed technology for manufacturing non-volatile tunable nanophoton chips is ready for implementation in microelectronic production without additional upgrades.

    A team of scientists from MIET and Moscow State University has created fully optical tunable ring microresonators based on silicon nitride and thin films of one of the so — called phase memory materials-Ge-Sb-Te (GST). The main feature of these materials is the change in optical and electrical properties when switching between amorphous (disordered) and crystalline (ordered) states.

    "In the chip we developed, the surface of silicon nitride ring microresonators is locally coated with a thin GST film. A change in the phase state of the GST coating and, consequently, its absorption leads to a change in the optical signal passing through the waveguide. Switching of phase states can be initiated by laser pulses passing through a waveguide, " said Petr Lazarenko, a senior researcher at the Institute of Advanced Materials and Technologies of the National Research University MIET.

    Phase state switching occurs in 10 nanoseconds, and GST film is one of the most optimal materials for controlling signals in thin-film waveguide elements that are used in telecommunications devices.

    According to the specialists of the research group, the technology they have developed for manufacturing non-volatile tunable nanophoton chips is fully ready for implementation in microelectronic production, since it can be fully implemented using standard CMOS technology processes and does not require additional modernization of installations.

    Now the research team is optimizing the chip to increase the number of recorded logic levels. The research group also develops approaches to designing new integrated optical circuits and systems based on them.

    ____________________________________________________________________________________________________________________________________________________________________________________________

    https://sdelanounas.ru/blogs/145210/

    A new processor of the original architecture has been created in Russia. Not "Elbrus" and not"Baikal"

    A universal processor for performing computationally complex cryptographic transformations and, in particular, blockchain transactions with extreme energy efficiency.

    Organized ten years ago at Moscow State University, the Malt System microelectronic design center developed and registered with Rospatent a processor with its own architecture for streaming network traffic processing.

    Processors for energy-efficient solution of mathematical physics problems that require irregular memory access.

    The Russian multi-core processor development team, Malt System, has passed the procedure for registering the topology of its new processor, having received a certificate from Rospatent.

    In the company's model range, the novelty has the name Malt-Cv3, its commercial name is "Enceladus" (the name of one of the titans in ancient Greek mythology, which migrated to the sixth-largest satellite of Saturn).

    According to the developers, Enceladus is designed for streaming network traffic processing at speeds up to 1 Gbit / s, including ensuring the security of network connections "by software encryption/decryption of traffic using any domestic or foreign algorithms."

    The company calls the chip the third in a line of Malt-C processors designed to perform complex cryptographic transformations, and the first "embedded and extremely compact". The latter circumstance is explained by the fact that it will have dimensions of no more than 9×9 mm in a BGA-type case (English Ball Grid Array, array of balls). "This is less than the RJ-45 connector," the developers note. — Such a processor can really be integrated into almost any device."

    Enceladus is designed using 16 nm technology. Malt System announced its creation in mid-May 2020. The company announced placing an order for the production of chips at TSMC's contract Taiwanese factory on July 30, 2021. Developers hope to receive samples "in silicon" in the first quarter of 2022. The release of the SDK and debugging board for Enceladus is scheduled for the third quarter of 2022.

    Processors for parallel operation with large data sets that are stored in RAM or external memory and are characterized by complex processing logic.

    Chip architecture and characteristics

    The company notes that Enceladus is built on its own original Malt architecture. It is based on dozens or hundreds, depending on the model, of compact asynchronous universal computing cores connected by one or several original worm-hole networks with a fat-tree topology, the developers describe their architecture.

    "Communication between networks is hardware and software," they say. - The hierarchy of universal cores includes three levels: supermaster — control core, master-communication cores, slave-computing cores available for user tasks. Slave cores can contain vector accelerators that perform specialized tasks of the target class. Each accelerator contains from eight to 128 processor elements of the same type with shared instruction memory. All computing cores and accelerators have their own local data memory. All generic cores directly address shared external dynamic DRAM memory and other shared resources (PCIe, Ethernet, SATA)."

    Directly in Enceladus, four computing clusters are organized, each of which contains 16 specialized cores and is controlled by one universal RISC core. The chip contains two 1GEb Ethernet controllers, seven general-purpose RISC processor cores, three SIMD accelerator blocks, a shared static memory block, and SPI-Flash, UART, and GPIO controllers.

    Interaction with the processor is carried out via universal interfaces SPI, UART, GPIO, which are also controlled by a single dedicated universal core. 512 KB of shared static SRAM memory will be available on the chip, and it is also planned to support up to 64 MB of external HyperRAM/HyperFlash memory.

    The estimated operating frequency of the processor will be 1.2 GHz. The chip implements an IP frequency generator unit with automatic tuning without pulse interference FDPLL. The projected power consumption of the new product at full load should not exceed 3 watts. In typical modes, depending on the implemented algorithm, the power consumption should be in the range of 500-2000 MW.

    Development status

    MALT-Cv1-manufactured and tested samples in silicon.

    MALT-Cv2-manufactured and tested samples in silicon.

    MALT-Cv3 - currently in the RTL description debugging stage.

    https://maltsystem.ru/ru/product/malt-processors#malt-d

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    rigoletto


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    Post  rigoletto Thu Jan 20, 2022 6:37 pm

    GarryB, kvs, miketheterrible and lancelot like this post

    miketheterrible
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    Post  miketheterrible Fri Jan 21, 2022 4:57 pm

    Very good and informative video, thank you!

    I look forward to future developments from MCST, Baikal and the makers of KOMDIV.
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    rigoletto


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    Post  rigoletto Fri Jan 21, 2022 6:42 pm

    miketheterrible wrote:Very good and informative video, thank you!

    I look forward to future developments from MCST, Baikal and the makers of KOMDIV.

    This is good to know MCST already have some ideas about the development of a graphics card.

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    kvs
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    Post  kvs Fri Jan 21, 2022 6:46 pm

    rigoletto wrote:https://www.youtube.com/watch?v=-ojbRZnJkJo&t=59s

    So the MCST R series processors are all domestic Russian designs that use the SPARC command set. They
    are not clones.

    Funny how the interviewer "points out" that the Elbrus design is old. I know he is doing this for clarification but
    it is really a stupid idea. On this basis the x86 and RISC designs are all 40+ years out of date. These are
    instruction sets and processing paradigm like VLIW which can be considered timeless. It is how they are
    rendered into transistors and the tech process for the actual hardware that marks progress.

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    miketheterrible
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    Post  miketheterrible Fri Jan 21, 2022 6:53 pm

    Im curious if any of them will move to RISC-V?

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